Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) and programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure, which typically includes large numbers of interconnect lines interconnected by programmable interconnect points (PIPs). Some FPGAs also include additional logic blocks with special purposes (e.g., DLLs, RAM, processors, and so forth).
The interconnect structure, CLBs, IOBs, and other logic blocks are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the logic blocks and interconnect are configured. The configuration data can be read from memory (e.g., an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In some CPLDs, configuration data is stored on-chip in non-volatile memory. In other CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
For all of these PLDs, the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static RAM cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
As PLDs increase in complexity and size, the number of configuration bits required to program the devices increases significantly. Configuration bitstreams for some FPGAs, for example, are so large that the configuration of the FPGA becomes a significant factor in the initialization of a system. Additionally, the testing process for a PLD typically requires the loading of a large number of configuration bitstreams into the PLD, with tests being performed on the PLD after each configuration. Tester time is expensive, and an inefficient test process requiring a long series of time-consuming configuration steps can significantly increase the cost of a PLD. Therefore, it is desirable to provide methods of reducing bitstream size in order to reduce the configuration time for larger PLDs, both in a testing environment and in the systems that include the PLD after test.